Frequency dividers are an integral part of communications integrated circuits (ICs), particularly for broadband applications. As technology advances, ICs are manufactured with smaller transistors, and lower supply voltages are provided to the ICs. However, the lower supply voltages may cause problems for many conventional frequency divider circuits.
One common and conventional frequency divider is referred to as a current mode logic (CML) divider circuit. CML dividers include resistors that generate a voltage drop. Increasing the gain and decreasing the swing time of a CML divider is achieved at the expense of increased voltage drop across the resistors, which restricts the lowest operational supply voltage for a CML divider.
One alternative is a divider circuit having flip-flops that are biased to create operation points based on the input frequency of the signal being divided, such as disclosed in U.S. Pat. No. 7,683,682 to Won. Won discloses a body bias generator, for NMOS and PMOS transistors in the divider circuit, that generates a bias voltage based on a difference between a frequency of an input signal for dividing and a frequency of an internal reference signal. The input signal is coupled to a gate terminal of transistors in the flip-flops. The bias voltage is then applied to the body input of the PMOS and NMOS transistors to decrease power consumption by the transistors when the input signal has a low frequency and increase operation speed of the transistors when the input signal has a high frequency. The divider circuit of Won allows scaling of power consumption by the transistors when demand on the transistors is lower, however the body biasing of Won does not allow a reduction in operational supply voltage for the divider.
Another alternative for low supply voltage divider circuits includes dividers referred to as injection lock dividers. However, injection lock dividers occupy large die areas and are bandwidth-limited in operation. Thus, they are generally not suitable for broadband applications.